(1) Field of the Invention
The present invention relates to a semiconductor device in which two circuits are driven by two power supplies having different potentials.
For example, the present invention can be applied to a level shifting circuit using complementary metal-insulator semiconductor (CMIS) circuits in an erasable programmable read-only memory (EPROM).
(2) Description of the Prior Art
For example, in an EPROM, in order to reduce power dissipation, peripheral circuits such as address buffers, address decoders, level shifting circuits, and the like are constructed with complementary metal-oxide semiconductor (CMOS), broadly, CMIS, circuits. In such an EPROM, the read operation is performed using a low voltage of, for example, 5 volts, while the write operation is performed using a high voltage of, for example, 20 volts, to inject carriers into the floating gate thereof.
Assume that different voltages in response to the read operation and the write operation are applied to the same power supply terminal. In this case, since a high voltage is applied to the entire device during the write operation, all the circuit elements used in the device are required to withstand this high voltage, which is not preferable in view of integration density, reliability characteristics, and the like.
In a prior art device, during the write operation, only the circuit elements requiring a high voltage are driven by the high voltage, the other circuit elements being driven by a low voltage.
The above-mentioned prior art device, however, has a problem in that the sequence of supplying power is restricted. This restriction will be explained in detail later.